|Office Hours||Tuesday Noon to 1:00 and Friday, 1-2 PM|
My office is SB A-222 (down the hall from the Computer Science Department office).
|Required Text||Tanenbaum, A. S.|
Structured Computer Organization, Fourth Edition.
Prentice Hall, 1999. ISBN 0-13-095990-1.
(Percentages are approximate!)
|Homework and/or Quizzes||10%|
|Exams 1, 2, & 3||30% each|
|1||August 31||Course Introduction and Scope.
Review of Computers and Programming.
[ Units of Measure ]
|2||Sept 3||Layers of Abstraction.
Measures of Performance.
|Be prepared to discuss all exercises at the end of Chapter 1.
Whose name is associated with the architecture shown on the board in Tuesday's class?
|3||Sept 7||Information Encoding||Read Chapter 2|
|4||Sept 10||Information Encoding, continued
I/O Devices; Error Correcting Codes
|5||Sept 14||Memory Concepts|
|6||Sept 17||Primary and Secondary Memory Principles||[ Homework 1 Due ]|
|7||Sept 24||Digital Logic||Read Chapter 3|
|8||Sept 27||Digital Logic, continued|
|9||Oct 1||Decoders, Multiplexers, PLAs|
|10||Oct 5||ALU Design||[ Homework 2 Due ]|
|11||Oct 8||ALU Design, continued||[ Homework 3 Due ]|
|12||Oct 12||First Exam|
|13||Oct 15||Sequential Logic|
|14||Oct 19||Flip-Flops and Registers|
|15||Oct 22||Memory Design||[ Homework 4 Due ]|
|16||Oct 26||Busses and Interrupts|
|Oct 27||End of P/NC and unevaluated withdrawal period|
|17||Oct 29||Device Controller Design||[ Homework 5 Due ]|
|18||Nov 2||Busses and Device Controllers|
|19||Nov 5||Interrupt Processing|
|20||Nov 9||Datapath clock cycle timing.|
|21||Nov 12||MIC-1 Register Design|
|22||Nov 16||Condition Code Bits. Microinstruction format.|
|23||Nov 19||Microinstructions||[ Homework 6 Due ]|
|24||Nov 23||Second Exam
Class notes, plus sections 3.3 through 4.2 and Appendix A.
|25||Nov 30||Microprogramming the IADD instruction|
|26||Dec 3||Microinstruction format; microprogramming.|
|27||Dec 7||ILOAD and Microcode continued.||[ Homework 7 Due ]|
|28||Dec 10||Wide Load; Speeding up MIC-1||[ End of Term Information ]|
11:00 AM to 1:00 PM