| Office | NSB A-222 | |
| Phone | 997-3508 | |
vickery at babbage dot cs dot qc dot edu
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| Office Hours | Tuesday and Friday, 1-2 PM | |
| Course URL | http://babbage.cs.qc.edu/courses/cs341
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| Required Text | Patterson, D. A., and Hennessey, J. L. Computer Organization & Design, Second Edition. Morgan-Kaufmann, 1998. ISBN 1-55860-428-6. [A list of errata for the first printing of the book (beige cover)]. [Get Acrobat Reader to read the errata]. | |
| Grading (Percentages are approximate!) | ||
| Homework | 10% | |
| Exams 1, 2, & 3 | 30% each | |
| Class No. | Date | Topic | Assignment |
| 1 | Sept 1 | Course Introduction and Scope Review of Computers and Programming | Chapter 1 |
| 2 | Sept 4 | Technical Measurements; Information Encoding | |
| 3 | Sept 8 | Information Encoding continued | Chapter 2 [Homework 1] Due. [ Solutions ] |
| 4 | Sept 11 | Performance Measurement | |
| 5 | Sept 15 | Performance Measurement continued | Chapter 3 |
| 6 | Sept 18 | MIPS Architecture | [Homework 2] Due. |
| 7 | Sept 25 | MIPS Machine and Assembly Language R and I Format Instructions | |
| 8 | Oct 2 | MIPS Machine and Assembly Language Branch and Jump Instructions | |
| 9 | Oct 6 | MIPS Programming | [Homework 3] Due. |
| 10 | Oct 9 | First Exam Chapters 1-3 | |
| 11 | Oct 13 | Encoding Numbers Integers and IEEE-754 Floating-Point | Sections 4.1 through 4.4, and 4.8 |
| 12 | Oct 16 | Integer and Floating-Point Encoding continued. | Appendix B.1 through B.3 |
| 13 | Oct 20 | Gates: Logical and Electrical Properties. | [Homework 4] Due. |
| 14 | Oct 23 | Decoders, Multiplexors, Adders. | |
| 15 | Oct 27 | Decoders, Multiplexors, and Adders continued. | |
| 16 | Oct 30 | Logic Networks, Truth Tables, and Logic Equations Sum of products implementation. Karnaugh Maps. | [Homework 5] Due. |
| 17 | Nov 3 | Programmable Logic Devices | Chapter 4: Section 4.5. |
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Nov 4 | Last Day to Drop Without Penalty | ||
| 18 | Nov 6 | Parallel ALU Design. | Appendix B: Sections B.4 and B.5 |
| 19 | Nov 10 | Parallel ALU Design, continued. | [Homework 6] Due. |
| 20 | Nov 13 | Carry Lookahead Logic | |
| 21 | Nov 17 | Exam Review, Latches | |
| 22 | Nov 20 | Second Exam Chapter 4, Appendix B. | |
| 23 | Nov 24 | Register File Design. | |
| 24 | Dec 1 | Flip-Flops, Memory System, and SRAM IC Design. | [ Memory System Supplement ] |
| 25 | Dec 4 | MIPS Single Cycle Datapath. | Chapter 5: Sections 5.1 - 5.3 |
| 26 | Dec 8 | Generating Single Cycle Control Signals | [ Homework 7 ] Due. |
| 27 | Dec 11 | Generating ALUop and Multiple Cycle State Control | Appendix B, Section B.6 |
| 28 | Dec 15 | Multiple Cycle Control Signals | Appendix C, Figures C.3, C.5, C.7 |
| 29 | Dec 17 | Multiple Cycle Control Signals continued | |
| 30 | Dec 22 | Third Exam [ Study Guide ] | |