Class Number | Date | Topic | Assignment |
---|---|---|---|

1 | February 1 | von Neumann Architecture | Read Chapter 1 |

2 | February 4 | Cache Design
Units of Measure: memory, time, frequency | Read Chapter 2 |

3 | February 8 | Comparing Processor and Computer System Speeds
Data Path Cycle | Homework 1 Due:
Chapter 1 Exercises 1, 2, 3, 4, 5, 6, 10, and 11. |

4 | February 15 | Information Encoding: Fixed-point
Crooked Dice and Fire Alarms | Read Appendices A and B
[ Floating-Point Calculators ] |

5 | February 18 | Information Encoding: Floating-point | Homework 2 Due:
Chapter 2 Exercises 1, 2, 3, 7, 9, 11, 12. |

6 | February 22 | Floating-Point Examples
ASCII and ANSI Text Codes | Homework 3 Due:
Appendix A Exercises 1, 2, 4, 7, 9, 14. Appendix B Exercises 1, 2 (show work!), 5 (check using web pages). |

7 | February 25 | Encoding Visual Information. | |

8 | February 29 | Encoding Auditory Information. | |

9 | March 3 | ISDN: baud rate vs bit rate.
Error Detection and Correction Hamming Codes | |

10 | March 7 | Disks and CDs.
[ After Class ] | Homework 4 Due:
Chapter 2 Exercises 18, 19, 20, 22, 24, 25. |

11 | March 10 | *** Exam 1 ***
| |

12 | March 14 | Introduction to Gates and Logic Design
Minimization | Read Chapter 3. |

13 | March 17 | Exam post-mortem
Decoders | |

14 | March 21 | Multiplexors | Homework 5 Due:
Chapter 3, Exercises 1, 2, 3, 4, 5, 6, 7, 8, 9, 10. |

15 | March 24 | Half adders, full adders
parallel adders. | |

16 | March 28 | Carry Lookahead Logic | |

March 28 | Last Day to Withdraw Without
Penalty
| ||

17 | March 31 | ALU Design | |

18 | April 4 | Programmable Logic Devices | |

19 | April 7 | PAL and PROM Structures
NOR Latch Operation | Review Chapter 3, Exercises 11 through 16 for the next exam. |

20 | April 11 | Clocked Latch Design
Datapath Clocking | |

21 | April 14 | Flip-Flops
SRAM Design | |

22 | April 18 | Memory Structures | Homework 6 Due:
Chapter 3, Exercises 17, 19, 20, 22, 23, 24. |

April 19 through 28 | Spring Break
| ||

23 | May 2 | Review for Exam; busses. | Homework 7 Due:
Chapter 3, Exercises 25, 26, 28, 32, 35, 40. |

24 | May 5 | *** Exam 2 ***
| |

25 | May 9 | Bus timing for memory read. | |

26 | May 12 | Busses and I/O Interfacing | |

27 | May 16 | IJVM Data Path | |

28 | May 19 | Control of IJVM Data Path | |

May 23 | *** Final Exam ***
11:00 to 1:00 [ Study Guide ] [ Extra Credit Assignment ] Due [ Alternate Extra Credit Assignment ] Due |